Current lithography process control evaluates critical dimensions (CDs), overlay, side wall angles (SWA), focus and dose etc. and is carried out after the lithography process is completed, i.e., after the process on the track, the application of the lithography tool (e.g., scanner, stepper) and additional and track processes (e.g., develop) have taken place. The associated metrology processes are used to detect need for rework and scanner correction terms, e.g., in a feedback mode. Current process control is carried out by stand-alone tools or by track-integrated tools, which are operated in similar manners.
Advanced nodes technology has very limited overlay budgets that dictate narrow process windows of 4 nm and below. Currently the overlay (OVL) is measured after the process in the lithography cell, and the data is used for calculating rework disposition and scanner correction terms. The alignment of the current exposure to previous exposure is being done using alignment marks that are printed on the wafer in a previous exposure. The overlay is measured on a different target, that includes at least two features, one is printed in the previous layer and one in the current.
Before and during the wafer exposure the scanner is looking for the alignment marks and calculates their location, by doing that the scanner aligns the previous layer pattern with new layer pattern it is about to be printed. The method of measurement and the algorithm that is being used to calculate the location of the target might be sensitive to process induced errors. Stated differently, the asymmetry of the feature's profile in the alignment mark might create a systematic error in the alignment of the wafer. If this process-induced asymmetry is changing along the wafer, it may induce a within-wafer (and even within-field) overlay variation. Currently those errors are being detected by carrying out overlay measurements after the development process in the lithography cell. If the wafers fail specific criteria, they go through a rework process in which the resist and other layers on the wafer (e.g., BARC—the bottom anti-reflective coating layer) are stripped and cleaned and the wafers are returned for subsequent lithographic processing. The rework process is time consuming, reduces the die yield, and may have other costs.